DK-DEV-5SGXEA7N【PDF 288/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51013

2013.05.06

Temperature Sensing Diode

11-3

Altera recommends that you power down unused PCIe HIPs, per side, by connecting the PCIe HIP power

to GND on the PCB for additional power savings. All of the HIPs on a side of the device must be unused to

be powered down. For additional information refer to the pin connection guidelines.

Table 11-1: Programmable Power Capabilities for Stratix V Devices

This table lists the available Stratix V programmable power capabilities. Speed grade considerations can add to the

permutations to give you flexibility in designing your system.

LAB

Routing

Memory Blocks

DSP Blocks

Clock Networks

Feature

Programmable Power Technology

Yes

Yes

Fixed setting (27)

Fixed setting (27)

No

Related Information

? Stratix V E, GS, and GX Device Family Pin Connection Guidelines

Provides more information about powering down PCIe HIPs.

? Stratix V GT Device Family Pin Connection Guidelines

Provides more information about powering down PCIe HIPs.

Temperature Sensing Diode

The Stratix V TSD uses the characteristics of a PN junction diode to determine die temperature. Knowing

the junction temperature is crucial for thermal management. You can calculate junction temperature using

ambient or case temperature, junction-to-ambient (ja) or junction-to-case (jc) thermal resistance, and device

power consumption. Stratix V devices monitor its die temperature with the internal TSD with built-in

analog-to-digital converter (ADC) circuitry or the external TSD with an external temperature sensor. This

allows you to control the air flow to the device.

Internal Temperature Sensing Diode

You can use the Stratix V internal TSD in the following operations:

? Power-up mode — to read the die's temperature during configuration, enable the ALTTEMP_SENSE

megafunction in your design.

? User mode — to read the die's temperature during user mode, assert the clken signal to the internal TSD

circuitry.

Note: To reduce power consumption, disable the Stratix V internal TSD when you are not using it.

(27)

Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By

default, unused DSP blocks and memory blocks are set to low-power mode.

Power Management in Stratix V Devices

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